SH7205 Datasheet, PDF (703/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Compare Match Timer (CMT)
Section 13 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer module (CMT) consisting of two units of two-
channel 16-bit timers, which makes a total of four channels. The CMT has a 16-bit counter, and
can generate interrupts at set intervals.
13.1 Features
• Independent selection of four counter input clocks at two channels
Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected.
• Selection of DMA transfer request or interrupt request generation on compare match by
DMAC setting
• When not in use, the CMT can be stopped by halting its clock supply to reduce power
consumption.
Figure 13.1 shows a block diagram of CMT.
CMI2
CMI0
Pφ/8 Pφ/32 Pφ/128 Pφ/512
CMT2, CMT3
CMT0,
CMT1
Control circuit
Clock selection
CMI3
CMI1
Pφ/8 Pφ/32 Pφ/128 Pφ/512
Control circuit
Clock selection
Channel 0
Module bus
Channel 1
Bus
interface
[Legend]
CMSTR:
CMCSR:
CMCOR:
CMCNT:
CMI:
Compare match timer start register
Compare match timer control/status register
Compare match constant register
Compare match counter
Compare match interrupt
Figure 13.1 Block Diagram of CMT
Peripheral bus
Rev. 1.00 Mar. 25, 2008 Page 671 of 1868
REJ09B0372-0100