SH7205 Datasheet, PDF (135/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 3 Floating-Point Unit (FPU)
These possibilities of each exceptional handling on floating-point operation are shown in the
individual instruction descriptions. All exception events that originate in the floating-point
operation are assigned as the same FPU exceptional handling event. The meaning of an exception
generated by floating-point operation is determined by software by reading from FPSCR and
interpreting the information it contains. Also, the destination register is not changed when FPU
exception handling operation occurs.
Except for the above, the FPU disables exception handling. In every processing, the bit
corresponding to source V, Z, O, U, or I is set to 1, and a default value is generated as the
operation result.
• Invalid operation (V): qNaN is generated as the result.
• Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
• Overflow (O):
When rounding mode = RZ, the maximum normalized number, with the same sign as the
unrounded value, is generated.
When rounding mode = RN, infinity with the same sign as the unrounded value is generated.
• Underflow (U):
Zero with the same sign as the unrounded value is generated.
• Inexact exception (I): An inexact result is generated.
Rev. 1.00 Mar. 25, 2008 Page 103 of 1868
REJ09B0372-0100