SH7205 Datasheet, PDF (866/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
(3) Data Reception
Figure 17.15 shows an example of reception operation, and figure 17.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an SSRXI interrupt is generated. The
RDRF bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (SSERI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
SSCK
SSO
RDRF
Bit 0
1 frame
Bit 7
Bit 0
1 frame
Bit 7
Bit 0
Bit 7
LSI operation
User operation Dummy-read SSRDR
SSRXI interrupt
generated
SSRXI interrupt
generated
Read data from SSRDR
SSRXI interrupt
generated
Read data from SSRDR
Figure 17.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
Rev. 1.00 Mar. 25, 2008 Page 834 of 1868
REJ09B0372-0100