SH7205 Datasheet, PDF (957/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
When an underflow or overflow error condition has matched, the CHNO [1:0] bit and the SWNO
bit can be used to recover the SSIF module to a known status. When an underflow or overflow
occurs, the host can read the channel number and system word number to determine what point the
serial audio stream has reached. In the transmitter case, the host can skip forward through the data
it wants to transmit until it finds the sample data that matches what the SSIF module is expecting
to transmit next, and so resynchronize with the audio data stream. In the receiver case the host
CPU can store null data to make the number of receive data items consistent until it is ready to
store the sample data that the SSIF module is indicating will be received next, and so
resynchronize with the audio data stream.
19.4.6 Serial Bit Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD = 0), the SSIF module is in clock slave mode and
the shift register uses the bit clock that was input to the SSISCK pin.
If the serial clock direction is set to output (SCKD = 1), the SSIF module is in clock master mode,
and the shift register uses the oversampling clock or a divided oversampling clock as the bit clock.
The oversampling clock is divided by the ratio specified by the serial oversampling clock division
ratio bits (CKDV) in SSICR for use as the bit clock by the shift register.
In either case the module pin, SSISCK, is the same as the bit clock.
Rev. 1.00 Mar. 25, 2008 Page 925 of 1868
REJ09B0372-0100