SH7205 Datasheet, PDF (353/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(6) Initialization Sequencer
SDRAMC is provided with a sequencer for issuing the commands for SDRAM initialization. The
initialization sequence should always be initiated a single time only following a reset (all
channels) or following recovery from deep-power-down mode (individual channels). No normal
operation is guaranteed if the initialization sequence is not performed or is performed more than
once.
The SDRAM initialization sequencer issues the precharge-all-banks command and n (n = 1 to 15)
auto-refresh commands in the stated order. Make timing settings for the initialization sequencer,
using SDRAM initialization register 0 (SDIR0). To initiate initialization sequences, use SDRAM
initialization register 1 (SDIR1).
Note that an initialization sequence for SDRAM0 and SDRAM1 is initiated simultaneously, using
the DINIRQ bit.
Figure 10.11 shows a timing example for the initialization sequence. Setting DARFC to 2 or
greater causes multiple initialization auto-refresh cycles to be performed.
CKIO
SDRAM command
Initialization precharge cycle
Initialization
auto-refresh cycle
PRA DSL DSL DSL RFA DSL DSL DSL
DPC
DARFI
DSL: Deselect command
RFA: Auto-refresh command
PRA: Precharge-all-banks command
DINST bit value
changes to 0
Figure 10.11 Initialization Sequence Timing Example
(DPC Bits = 001, DARFI Bits = 0001, DARFC Bits = 001)
Rev. 1.00 Mar. 25, 2008 Page 321 of 1868
REJ09B0372-0100