SH7205 Datasheet, PDF (1332/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
25.2 Input/Output Pins
Table 25.1 Pin Configuration
Signal
ATAPI
Specification I/O
Function
IDED[15:0] DD[15:0]
I/O
Bidirectional data bus
IDEA[2:0] DA[2:0]
Output
Address bus
IODACK# DMACK#
Output
Primary channel DMA acknowledge (active low)
IODREQ DMARQ
Input
Primary channel DMA request (active high)
IDECS#[1:0] CS0#, CS1# Output
Primary channel chip select (active low)
IDEIOWR# DIOW#, STOP Output
Primary channel disk write (active low)
IDEIORD#
DIOR#,
HDMARDY#,
HSTROBE
Output
Primary channel disk read (active low)
IDEIORDY
IORDY,
DDMARDY#,
DSTROBE
Input
Primary channel ready signal (active high)
IDEINT
INTRQ
Input
Primary channel interrupt request* (active high)
IDERST# RESET#
Output
Primary channel ATAPI device reset (active low)
DIRECTION 
Output
External level shifter direction signal (0 when writing
to the device)
Note: * The ATAPI interface treats the interrupt signal from the ATAPI device as a level-
triggered input.
Rev. 1.00 Mar. 25, 2008 Page 1300 of 1868
REJ09B0372-0100