SH7205 Datasheet, PDF (193/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.2 Input/Output Pins
Table 7.1 shows the pin configuration of the INTC.
Table 7.1 Pin Configuration
Pin Name
Nonmaskable interrupt input
pin
Interrupt request input pins
Symbol
NMI
I/O
Input
IRQ7 to IRQ0 Input
PINT7 to PINT0 Input
Function
Input of nonmaskable interrupt
request signal
Input of maskable interrupt request
signals
7.3 Register Descriptions
The INTC has the following registers. These registers are used to set the interrupt priorities and
control detection of the external interrupt input signals. The registers are classified as the
following: CPU0-dedicated, CPU1-dedicated, and shared.
(1) CPU0-Dedicated Registers
Table 7.2 CPU0-Dedicated Register Configuration
Register Name
Interrupt control register 0
Interrupt control register 1
Interrupt control register 2
IRQ interrupt request register
PINT interrupt enable register
PINT interrupt request register
Bank control register
Bank number register
Interrupt priority register 01
Interrupt priority register 02
Interrupt priority register 05
Initial
Abbreviation R/W Value
C0ICR0
R/W *¹
C0ICR1
R/W H'0000
C0ICR2
R/W H'0000
C0IRQRR R/(W)*² H'0000
C0PINTER R/W H'0000
C0PIRR
R
H'0000
C0IBCR
R/W H'0000
C0IBNR
R/W H'0000
C0IPR01
R/W H'0000
C0IPR02
R/W H'0000
C0IPR05
R/W H'0000
Address
H'FFFD9400
H'FFFD9402
H'FFFD9404
H'FFFD9406
H'FFFD9408
H'FFFD940A
H'FFFD940C
H'FFFD940E
H'FFFD9418
H'FFFD941A
H'FFFD9420
Access Size
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
Rev. 1.00 Mar. 25, 2008 Page 161 of 1868
REJ09B0372-0100