SH7205 Datasheet, PDF (1420/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
VIHSYNC
VIVSYNC
VIDATA[7:0]
VICLKENB
VICLK
Field
determination
YCbCr422
↓
YCbCr444
↓
RGB conversion
Resizing
(only in horizontal
direction)
Data buffer
SE buffer (Double-buffer structure)
(16 bits × 512 words × 2 planes)
Conversion of pixel format (16 → 22)
α → 4 bits + RGB → 666 (18 bits)
α blending
Output control
DCLKIN
CSYNC
DAC
Panel unit
RGB
Figure 26.3 Block Diagram of the Output Block
Rev. 1.00 Mar. 25, 2008 Page 1388 of 1868
REJ09B0372-0100