SH7205 Datasheet, PDF (299/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.3 Area Overview
10.3.1 Address Map
In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled,
cache-disabled, and on-chip spaces (on-chip high-speed RAM, on-chip RAM for data retention,
on-chip peripheral modules, and reserved areas) according to the upper bits of the address.
External address spaces CS5 to CS0, SDRAM0, and SDRAM1 are cache-enabled when internal
address A29 = 0 and cache-disabled when A29 = 1.
The kind of memory to be connected and the data bus width are specified independently for each
partial space. The address map for the external address space is shown below.
Table 10.2 Address Map
Internal Address
Space Memory to be Connected
H'00000000 to H'03FFFFFF CS0
Normal space
H'04000000 to H'07FFFFFF CS1
Normal space
H'08000000 to H'0BFFFFFF CS2
Normal space
H'0C000000 to H'0FFFFFFF CS3
Normal space
H'10000000 to H'13FFFFFF CS4
Normal space
H'14000000 to H'17FFFFFF CS5
Normal space
H'18000000 to H'1BFFFFFF SDRAM0 SDRAM space
H'1C000000 to H'1FFFFFFF SDRAM1 SDRAM space
H'20000000 to H'23FFFFFF CS0
Normal space (shadow)
H'24000000 to H'27FFFFFF CS1
Normal space (shadow)
H'28000000 to H'2BFFFFFF CS2
Normal space (shadow)
H'2C000000 to H'2FFFFFFF CS3
Normal space (shadow)
H'30000000 to H'33FFFFFF CS4
Normal space (shadow)
H'34000000 to H'37FFFFFF CS5
Normal space (shadow)
H'38000000 to H'3BFFFFFF SDRAM0 SDRAM space (shadow)
H'3C000000 to H'3FFFFFFF SDRAM1 SDRAM space (shadow)
H'40000000 to H'7FFFFFFF Reserved Reserved area
H'80000000 to H'E7FFFFFF Reserved Reserved area
H'E8000000 to H'EBFFFFFF Other
On-chip peripheral modules
H'EC000000 to H'EFFFFFFF Reserved Reserved area
BIU*¹
Size Cache
BIU_E
64MB Cache-
64MB ^enabled
64MB
64MB
64MB
64MB
64MB
64MB
64MB Cache-
64MB ^disabled
64MB
64MB
64MB
64MB
64MB
64MB
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BIU_PB3 64MB
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Rev. 1.00 Mar. 25, 2008 Page 267 of 1868
REJ09B0372-0100