SH7205 Datasheet, PDF (342/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(3) External Wait Function
The external wait signal (WAIT) can be used to extend the wait cycle duration beyond the value
specified by the cycle wait (CSRWAIT, CSWWAIT) or page access cycle wait (CSPRWAIT,
CSPWWAIT) settings in the CSn wait control register (CSWCNTn). If external wait enable
(EWENB = 1) has been selected, wait cycles are inserted for as long as the WAIT signal remains
low level. The WAIT signal is disabled if external wait disable (EWENB = 0) has been selected.
Note that the wait cycles specified by the settings of the CSn wait control register (CSWCNTn)
are inserted regardless of the state of the WAIT signal.
(a) Normal Read/Write Operation
The WAIT signal is sampled all the time and its result is reflected two cycles later. Thus, when the
WAIT signal is low two cycles before the end of the wait cycles, external cycles are inserted.
After the WAIT signal has gone high, the wait cycles end two cycles later.
(b) Page Access Operation
The initial data read/write operation is the same as a normal read/write operation. That is, when
the WAIT signal is low two cycles before the end of the wait cycles (Tend), external wait cycles
are inserted. After the WAIT signal has gone high, the wait cycles end (Tend) two cycles later.
In the second and subsequent read accesses, the page wait cycle is extended if the WAIT signal is
low two cycles before the end of the page access wait cycle (Tend), and the page wait cycles end
(Tend) two cycles after the WAIT signal has gone high.
Figures 10.6 and 10.7 show examples of external wait timing for page read access by longword
(32-bit) access to a 16-bit channel. Figure 10.6 is an example in which one or more cycles of cycle
wait state or page cycle wait state has been set. Figure 10.7 is an example in which no cycle wait
or page cycle wait state has been set. Note that the value of the WAIT signal before the beginning
of the bus cycle is reflected if there are only a few cycles of cycle wait states.
Rev. 1.00 Mar. 25, 2008 Page 310 of 1868
REJ09B0372-0100