SH7205 Datasheet, PDF (332/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.17 SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT)
SDCKSCNT enables or disables the clock stop control signal (signal in the chip) and specifies the
number of assert cycles.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- DCKSEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
DCKSC[7:0]
0
0
0
0
0
1
1
1
1
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
31 to 17 
All 0
16
DCKSEN 0
15 to 8 
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Clock Stop Control Signal Enable
This bit is used to enable or disable the clock stop control
function. If enabled, the clock stop control function stops
CKIO (low level) at transition to or recovery from deep-
power-down mode. If disabled, the function does not stop
CKIO.
0: Clock stop control function disabled
1: Clock stop control function enabled
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 300 of 1868
REJ09B0372-0100