SH7205 Datasheet, PDF (843/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Initial
Bit
Bit Name Value R/W
0
CE
0
R/W
Section 17 Synchronous Serial Communication Unit (SSU)
Description
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave mode), an incomplete error
occurs because it is determined that a master device
has terminated the transfer.
In reception as the slave device in SSU mode, received
data (reading SSRDR) must be read out and RDRF in
SSSR cleared before reception of the next frame starts.
In transmission/reception as the slave device in SSU
mode, the data for transmission must be written (writing
to SSTDR) and TDRE in SSSR cleared before
transmission of the next frame starts. If either condition
is not met, an incomplete error will be generated at the
end of that frame.
Data reception does not continue while the CE bit is set
to 1. Serial transmission also does not continue. Reset
the SSU internal sequencer by setting the SRES bit in
SSCRL to 1 before resuming transfer after incomplete
error.
[Setting conditions]
• When a low level is input to the SCS pin in master
mode (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in
slave mode (the MSS bit in SSCRH is cleared to 0)
• In reception as the slave device, following a frame in
which reading of SSRDR and clearing of RDRF
were not completed by time the next frame started,
the end of the next frame.
• In transmission as the slave device, following a
frame in which writing to SSTDR and clearing of
TDRE were not completed by time the next frame
started, the end of the next frame
[Clearing condition]
• When writing 0 after reading CE = 1
Rev. 1.00 Mar. 25, 2008 Page 811 of 1868
REJ09B0372-0100