SH7205 Datasheet, PDF (1151/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.5 Interrupt Sources
The FLCTL has seven interrupt sources: Status error, ready/busy timeout error, ECC error, 4-
symbol ECC pattern generation end, transfer end, FIFO0 transfer request, and FIFO1 transfer
request. Each of the interrupt sources has its corresponding interrupt flag and the interrupt can be
requested independently to the CPU if the interrupt is enabled by the interrupt enable bit. Note that
the status error, ready/busy timeout error, ECC error, and 4-symbol ECC pattern generation end,
use the common FLSTE interrupt to the CPU.
Table 23.5 FLCTL Interrupt Requests
Interrupt Source Interrupt Flag Enable Bit Description
Priority
FLSTE interrupt
STERB
STERINTE Status error
Highest
BTOERB
RBERINTE Ready/busy timeout error
ECERB
ECERINTE ECC error
4ECCEND
4ECEINTE
4-symbol ECC pattern
generation end
FLTEND interrupt TREND
TEINTE
Transfer end
FLTRQ0 interrupt TRREQF0
TRINTE0
FIFO0 transfer request
FLTRQ1 interrupt TRREQF1
TRINTE1
FIFO1 transfer request
Lowest
Note: Flags for the FIFO0 overrun error/underrun error and FIFO1 overrun error/underrun error
also exist. However, no interrupt is requested to the CPU.
Rev. 1.00 Mar. 25, 2008 Page 1119 of 1868
REJ09B0372-0100