SH7205 Datasheet, PDF (1534/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 27 Pin Function Controller (PFC)
(4) Port H Control Register L1 (PHCRL1)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PH3MD[3:0]
PH2MD[3:0]
PH1MD[3:0]
PH0MD[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 12 PH3MD[3:0] 0000 R/W PH3 Mode
Select the function of the PH3.
11 to 8 PH2MD[3:0] 0000 R/W PH2 Mode
Select the function of the PH2.
7 to 4 PH1MD[3:0] 0000 R/W PH1 Mode
Select the function of the PH1.
3 to 0 PH0MD[3:0] 0000 R/W PH0 Mode
Select the function of the PH0.
27.2.17 Port J I/O Register L (PJIORL)
PJIORL is 16-bit readable/writable register that is used to set the pins on port J as inputs or
outputs. The PJ12IOR to PJ0IOR bits correspond to the PJ12 to PJ0 pins respectively. The setting
of PJIORL is valid for the pins for which general I/O function or TIOC I/O function of the MTU2
is selected. PJIORL has no effect on the pins for which other function is selected. If a bit in
PJIORL is set to 1, the corresponding pin on port J functions as an output pin. If it is cleared to 0,
the corresponding pin functions as an input pin.
Bits 15 to 13 in PJIORL are reserved. These bits are always read as 0. The write value should
always be 0.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
PJ12 PJ11 PJ10 PJ9 PJ8 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Mar. 25, 2008 Page 1502 of 1868
REJ09B0372-0100