SH7205 Datasheet, PDF (1172/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Table 24.5 USB Data Bus Line Status
LNST[1]
LNST[0]
During Low-
Speed
Operation
(only when
Host
Controller
Function is
Selected)
During Full-
Speed
Operation
During High-
Speed
During Chirp
Operation
Operation
0
0
SE0
SE0
Squelch
Squelch
0
1
K state
J state
Not squelch Chirp J
1
0
J state
K state
Invalid
Chirp K
1
1
SE1
SE1
Invalid
Invalid
[Legend]
Chirp:
The reset handshake protocol is being executed in high-speed operation enabled
state (HSE = 1).
Squelch: SE0 or idle state
Not squelch: High-speed J state or high-speed K state
Chirp J:
Chirp J state
Chirp K:
Chirp K state
Rev. 1.00 Mar. 25, 2008 Page 1140 of 1868
REJ09B0372-0100