SH7205 Datasheet, PDF (1175/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
5
RESUME
0
R/W PORT0 Resume Output
When the host controller function is selected, setting
this bit to 1 causes this module to drive PORT0 to
the K-state and perform the resume processing.
This module continues outputting K-state while
RESUME is 1. Ensure that RESUME stays 1 (=
resume period) for the time defined by USB
Specification 2.0.
0: Resume signal is not output.
1: Resume signal is output.
Note: This bit should be set to 1 only in the
suspended state. When the resume
processing has ended, write 0 to this bit and 1
to the UACT bit at the same time.
4
UACT
0
R/W PORT0 USB Bus Enable
When the host controller function is selected, setting
this bit to 1 causes this module to enable the USB
bus on PORT0 and perform SOF output and data
transmission and reception.
After this bit is set to 1, this module starts outputting
SOF/µSOF within 1 (µ) frame. When this bit is
cleared to 0, this module enters the idle state after
outputting SOF/µSOF.
0: Downstream port is disabled (SOF/µSOF
transmission is disabled).
This module clears this bit to 0 on any of the
following conditions.
• A DTCH interrupt is detected during
communication (while UACT = 1).
• An EOFERR interrupt is detected during
communication (while UACT = 1).
1: Downstream port is enabled (SOF/µSOF
transmission is enabled).
Note: Writing 1 to this bit should be done at the end
of the USB reset process (writing 0 to
USBRST) or at the end of the resume process
from the suspended state (writing 0 to
RESUME).
Rev. 1.00 Mar. 25, 2008 Page 1143 of 1868
REJ09B0372-0100