SH7205 Datasheet, PDF (438/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.13 DMA Interrupt Status Register (DMISTS)
DMISTS consists of DMA interrupt request status bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 18 DISTS0 H'0000 R
to
DISTS13
DMA Interrupt Request Status
These bits enable you to reference the occurrence status of a
common interrupt request for the interrupt controller.
0: No interrupt request occurred.
1: An interrupt request occurred.
• Condition for setting these bits to 1
If the DMA transfer end condition is detected when the
DMA common interrupt request signal control bit (DINTA) is
set to 1, the bits of the corresponding channel are set to 1.
The setting of the DMA interrupt control bit (DINTM) does
not affect this setting.
• Condition for clearing these bits to 0
17 to 0 
Clearing the DMA transfer end condition detect bit (DEDET)
of the DMA transfer end detection register (DMEDET)
corresponding to the channel where the interrupt occurred
to 0 clears these bits to 0 (for details, see section 11.5.2,
DMA Interrupt Requests).
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
Notes: 1. This register is read-only.
2. Bits 31 to 18 correspond to channels 0 to 13.
Rev. 1.00 Mar. 25, 2008 Page 406 of 1868
REJ09B0372-0100