SH7205 Datasheet, PDF (949/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

• Parallel Right-Aligned with Delay
Section 19 Serial Sound Interface with FIFO (SSIF)
As basic sample format configuration except PDTA = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA TD0 0 0 TD3 TD2 TD1 TD0 0 0 TD3 TD2 TD1 TD0 0 0 TD3
• Mute Enabled
Figure 19.17 Parallel Right-Aligned with Delay
As basic sample format configuration except MUEN = 1 (TD data ignored)
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19.18 Mute Enabled
Rev. 1.00 Mar. 25, 2008 Page 917 of 1868
REJ09B0372-0100