SH7205 Datasheet, PDF (160/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
5.5 Changing the Frequency
The frequencies of the internal clocks (I₀φ and I₁φ) and peripheral clock (Pφ) can be changed either
by changing the multiplication rate of the PLL circuit or by changing the division ratio of the
divider. All of these are controlled by software through the frequency control registers 0 and 1
(FRQCR0 and FRQCR1). The methods are described below.
The multiplication rate and division ratio must be changed so that the register values satisfy the
conditions shown in table 5.3. Otherwise, the operation is not guaranteed.
5.5.1 Changing the Multiplication Rate
An oscillation stabilization time is required when the multiplication rate of the PLL circuit is
changed. On-chip WDT0 counts the stabilization time. The oscillation stabilization time becomes
the same time as that of recovery from the software standby mode.
When changing the multiplication rate, after setting IFC1 and IFC0 in FRQCR1 to B'00 and
specifying CPU1 not to be interrupted, execute the SLEEP command from CPU1, confirm that
single processor 0 mode (CPU1 is in sleep mode) (for details, see section 30, Power-Down
Modes), and perform the following procedure from CPU0.
1. In the initial state, the multiplication rate of the PLL circuit is 12 times in clock modes 0, 1,
and 2 or 16 times in clock mode 3.
2. Set a value that will produce the specified oscillation stabilization time in WDT0 for CPU0
and stop WDT0. The following must be set:
WTCSR0.TME = 0: WDT stops
WTCSR0.CKS[2:0]: Division ratio for WDT counter clock
WTCNT0 counter: Initial counter value
(The WDT0 count is incremented using the clock after the setting.)
3. Set the desired value in the STC[1:0] bits of FRQCR0. The division ratios can also be set in
the IFC[1:0] and PFC[2:0] of FRQCR0.
4. This LSI pauses temporarily and WDT0 starts to increment. The internal and peripheral clocks
both stop and only WDT0 is supplied with the clock. The clock will continue to be output at
the CKIO pin. Low level output can also be selected by setting CKOEN2 of FRQCR0.
This state is the same as software standby mode. Whether or not registers are initialized
depends on the module. For details, see section 32.3, Register States in Each Operating Mode.
5. Supply of the clock that has been set begins at WDT0 count overflow, and CPU0 of this LSI
begins to operate again. WDT0 stops after it overflows. At this time, WOVF of WRCR0 is not
set. The counter (WTCNT0) stops at H'00.
Rev. 1.00 Mar. 25, 2008 Page 128 of 1868
REJ09B0372-0100