SH7205 Datasheet, PDF (841/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Initial
Bit
Bit Name Value R/W
6
ORER
0
R/W
5, 4 
All 0 R
3
TEND
0
R/W
Section 17 Synchronous Serial Communication Unit (SSU)
Description
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either.
However, this bit is invalid during the slave data receive
operation (MSS = 0 in SSCRH, and TE = 0 and RE = 1
in SSER) in SSU mode (SSUMS = 0 in SSCRL).
[Setting condition]
• When one byte of the next reception is completed
with RDRF = 1 (except the slave data receive
operation in SSU mode)
[Clearing condition]
• When writing 0 after reading ORER = 1
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit End
[Setting conditions]
• When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
• After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
[Clearing conditions]
• When writing 0 after reading TEND = 1
• When writing data to SSTDR
Rev. 1.00 Mar. 25, 2008 Page 809 of 1868
REJ09B0372-0100