SH7205 Datasheet, PDF (1384/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
Bit
13, 12
11, 10
9, 8
7, 6
5, 4
Initial
Bit name Value
R/W
DM1_DSEL 00
R/W
DM2_DSEL 00
R/W
DM34_DSEL 00
R/W

Undefined R
DM1_MSEL 01
R/W
Description
SE Buffer DMA Transfer Condition
These bits set the conditions for DMA transfer to the
SE buffer.
00: Single operand transfer
01: Continuous operand transfer
10: Reserved
11: Reserved
DC Buffer DMA Transfer Condition
These bits set the conditions for DMA transfer from
the DC buffer.
00: Single operand transfer
01: Continuous operand transfer
10: Reserved
11: Reserved
SA/SB Buffer DMA Transfer Condition
These bits set the conditions for DMA transfer to the
SA/SB buffer.
00: Single operand transfer
01: Continuous operand transfer
10: Reserved
11: Reserved
Reserved
The read value is undefined. The write value should
always be 0.
SE Buffer DMA Transfer Mode
These bits set the transfer mode for DMA transfer to
the SE buffer.
00: Cycle stealing transfer
01: Pipeline transfer
10: Reserved
11: CPU transfer
Rev. 1.00 Mar. 25, 2008 Page 1352 of 1868
REJ09B0372-0100