SH7205 Datasheet, PDF (427/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit
8
7, 6
5 to 0
Initial
Bit Name Value R/W
DRLOD 0
R/W

All 0 R
DCTG[5:0] 000000 R/W
Description
DMA Destination Address Reload Function Enable
This bit is used to select whether to reload the destination
address when the DMA transfer end condition is detected.
When this bit is cleared to 0, reloading is not performed. If
the DMA transfer end condition is detected when this bit is
set to 1, the contents of the DMA reload destination address
register (DMRDADRn) are reloaded to the DMA current
destination address register (DMCDADRn).
0: Destination address reload function disabled
1: Destination address reload function enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Request Source Select
These bits are used to set DMA request sources.
When selecting a DMA request source other than the
software trigger, DREQ0 to DREQ3 pins, USB_0, USB_1,
and 2DG, set the DMA transfer request enable bits in
DREQER0 to DREQER8 of the interrupt controller (INTC).
For how to set DREQER0 to DREQER8, see section 7,
Interrupt Controller (INTC).
000000: Software trigger
000001: DREQ0 pin
000010: DREQ1 pin
000011: DREQ2 pin
000100: DREQ3 pin
000101: USB_0
000110: USB_1
000111: CMT_0
001000: CMT_1
001001: CMT_2
001010: CMT_3
001011: MTU2_0
001100: MTU2_1
Rev. 1.00 Mar. 25, 2008 Page 395 of 1868
REJ09B0372-0100