SH7205 Datasheet, PDF (471/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.6 Suspending, Restarting, and Stopping of DMA Transfer
11.6.1 Suspending and Restarting of DMA Transfer
Clearing the DMAC module activate bit (DMST) of the DMA activation control register
(DMSCNT) to 0 enables you to suspend data transfer on all channels of the DMAC. Clearing the
DMA transfer enable bit (DEN) of DMA control register B (DMCNTBn) of the corresponding
channel to 0 also enables you to suspend data transfer on the channel.
If the DMST or DEN bit is cleared to 0 when single operand transfer is in progress in the unit
operand transfer condition or sequential operand transfer condition, DMA transfer is suspended
after single operand transfer has ended without reference to each transfer mode (cycle-stealing
mode or pipelined transfer mode).
If the DMST or DEN bit is cleared to 0 when DMA transfer is in progress in the non-stop transfer
condition, DMA transfer is not suspended and continues till the DMA transfer end condition is
detected (i.e., till the byte count reaches 0).
To restart the suspended channel, set the cleared DMST and DEN bits to 1 to restart DMA
transfer.
11.6.2 Stopping of DMA Transfer on Any Channel
To stop DMA transfer on any channel, suspend DMA transfer on that channel and write 1 to the
DMAC internal state clear bit (DSCLR) of DMA control register B (DMCNTBn) to initialize the
DMAC interior. In this case, only the internal state of the DMAC internal circuit is initialized;
each register is not initialized.
Rev. 1.00 Mar. 25, 2008 Page 439 of 1868
REJ09B0372-0100