SH7205 Datasheet, PDF (1272/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
9
ACLRM
8
SQCLR
7
SQSET
Initial
Value
0
0
0
R/W Description
R/W Auto Buffer Clear Mode*³
Enables or disables automatic buffer clear mode for
the pertinent pipe.
To delete the information in the FIFO buffer assigned
to the pertinent pipe completely, write 1 and then 0 to
this bit successively.
Table 24.14 shows the information cleared by
successive writing of 1 and 0 to this bit and the cases
in which clearing of the information is necessary.
0: Disabled
1: Enabled (all buffers are initialized)
R*¹/W*² Toggle Bit Clear*³
This bit should be set to 1 to clear the expected
value of the sequence toggle bit for the next
transaction of the pertinent pipe to DATA0.
When the host controller function is selected, setting
this bit to 1 for the pipe for bulk OUT transfer, this
module starts the next transfer of the pertinent pipe
with the PING token.
0: No effect
1: Specifies DATA0.
R*¹/W*² Toggle Bit Set*³
This bit should be set to 1 to set DATA1 as the
expected value of the sequence toggle bit for the
next transaction of the pertinent pipe.
0: No effect
1: Specifies DATA1.
Rev. 1.00 Mar. 25, 2008 Page 1240 of 1868
REJ09B0372-0100