SH7205 Datasheet, PDF (958/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
19.5 Usage Notes
19.5.1 Limitations from Overflow during Receive DMA Operation
If an overflow occurs while the receive DMA is in operation, the module should be restarted. The
receive buffer in the SSIF consists of 32-bit registers that share the L and R channels. Therefore,
data to be received at the L channel may sometimes be received at the R channel if an overflow
occurs, for example, under the following condition: the control register (SSICR) has a 32-bit
setting for both data word length (DWL2 to DWL0) and system word length (SWL2 to SWL).
If an overflow is confirmed with the overflow error interrupt or overflow error status flag (the
OIRQ bit in SSISR), write 0 to the EN bit in SSICR and DMEN bit to disable DMA in the SSIF
module, thus stopping the operation. (In this case, the controller setting should also be stopped.)
After this, write 0 to the OIRQ bit to clear the overflow status, set DMA again and restart the
transfer.
19.5.2 Note on Using Oversampling Clock
To use the externally input clock as the oversampling clock, refer to section 5.6.1, Note on
Inputting the External Clock, in which the terms EXTAL and XTAL pins should be replaced by
the AUDIO_X1 and AUDIO_X2 pins respectively.
To use the crystal resonator, refer to section 5.6.2, Note on Using a Crystal Resonator, in which
the terms EXTAL and XTAL pins should be replaced by the AUDIO_X1 and AUDIO_X2 pins,
respectively.
Also, see section 5.6.3, Note on the Resonator.
Rev. 1.00 Mar. 25, 2008 Page 926 of 1868
REJ09B0372-0100