SH7205 Datasheet, PDF (877/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 I²C Bus Interface 3 (IIC3)
Channel Register Name
Abbreviation R/W
3
I²C bus control register 1
ICCR1_3
R/W
I²C bus control register 2
ICCR2_3
R/W
I²C bus mode register
ICMR_3
R/W
I²C bus interrupt enable register ICIER_3
R/W
I²C bus status register
ICSR_3
R/W
Slave address register
SAR_3
R/W
I²C bus transmit data register ICDRT_3
R/W
I²C bus receive data register ICDRR_3
R/W
NF2CYC register
NF2CYC_3 R/W
Initial
Value Address
Access
Size
H'00 H'FFFEEC00 8
H'7D H'FFFEEC01 8
H'38 H'FFFEEC02 8
H'00 H'FFFEEC03 8
H'00 H'FFFEEC04 8
H'00 H'FFFEEC05 8
H'FF H'FFFEEC06 8
H'FF H'FFFEEC07 8
H'00 H'FFFEEC08 8
18.3.1 I²C Bus Control Register 1 (ICCR1)
ICCR1 is an 8-bit readable/writable register that enables or disables the I²C bus interface 3,
controls transmission or reception, and selects master or slave mode, transmission or reception,
and transfer clock frequency in master mode.
ICCR1 is initialized to H'00 by a power-on reset.
Bit: 7
6
5
ICE RCVD MST
Initial value: 0
0
0
R/W: R/W R/W R/W
4
TRS
0
R/W
3
0
R/W
2
1
CKS[3:0]
0
0
R/W R/W
0
0
R/W
Initial
Bit
Bit Name Value R/W Description
7
ICE
0
R/W I²C Bus Interface 3 Enable
0: This module is halted. (SCL and SDA pins function
as ports.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6
RCVD
0
R/W Reception Disable
Enables or disables the next operation when TRS is 0
and ICDRR is read.
0: Enables next reception
1: Disables next reception
Rev. 1.00 Mar. 25, 2008 Page 845 of 1868
REJ09B0372-0100