SH7205 Datasheet, PDF (1167/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Table 24.3 Register Bits Initialized by Clearing the USBE Bit to 0 (when Function
Controller Function is Selected)
Register Name
SYSSTS0, SYSSTS1
DVSTCTR0, DVSTCTR1
INTSTS0
USBADDR
USEREQ
USBVAL
USBINDX
USBLENG
Bit Name
LNST
RHST
DVSQ
USBADDR
bRequest, bmRequestType
wValue
wIndex
wLength
Table 24.4 Register Bits Initialized by Clearing the USBE Bit to 0 (when Host Controller
Function is Selected)
Register Name
DVSTCTR0, DVSTCTR1
FRMNUM
UFRMNUM
Bit Name
RHST
FRNM
UFRNM
Rev. 1.00 Mar. 25, 2008 Page 1135 of 1868
REJ09B0372-0100