SH7205 Datasheet, PDF (769/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.3 Transmit Shift Register (SCTSR)
SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register
(SCFTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After
transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into
SCTSR and starts transmitting again.
The CPU cannot read from or write to SCTSR directly.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
16.3.4 Transmit FIFO Data Register (SCFTDR)
SCFTDR is a 16-byte FIFO register that stores data for serial transmission. When the SCIF detects
that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR
into SCTSR and starts serial transmission. Continuous serial transmission is performed until there
is no transmit data left in SCFTDR. The CPU can write to SCFTDR at all times.
When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new
data is attempted, the data is ignored.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: W W W W W W W W
Rev. 1.00 Mar. 25, 2008 Page 737 of 1868
REJ09B0372-0100