SH7205 Datasheet, PDF (657/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 12.100 shows the timing in this case.
TCNT write cycle
T1 T2
Pφ
Address
TCNT address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 12.100 Contention between TCNT Write and Increment Operations
Rev. 1.00 Mar. 25, 2008 Page 625 of 1868
REJ09B0372-0100