SH7205 Datasheet, PDF (377/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Single write
CKIO
SDRAM command
ACT DSL WR PRA DSL
Data bus
d
DRCD
DWR
DPCG
(ACT-WR) (WR-PRA) (PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
DSL: Deselect command
PRA: Precharge-all-banks command
Note: If the interval set in DRAS is shorter than the period from when the WR command is issued
until the DWR interval elapses, the DWR setting is used.
Figure 10.39 Single Write Timing Example 2
Single write
CKIO
SDRAM command
ACT DSL WR DSL PRA DSL
Data bus
d
DRCD
(ACT-WR)
DWR
(WR-PRA)
DPCG
(PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
DSL: Deselect command
PRA: Precharge-all-banks command
Figure 10.40 Single Write Timing Example 3
Rev. 1.00 Mar. 25, 2008 Page 345 of 1868
REJ09B0372-0100