SH7205 Datasheet, PDF (1066/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 21 A/D Converter (ADC)
Figure 21.1 shows a block diagram of the A/D converter.
Module data bus
Peripheral bus
AVcc
AVref
AVss
10-bit
A/D
AN0
AN1
AN2
AN3
+
ADTRG,
–
Control circuit
conversion start
AN4
trigger from MTU2
AN5
Comparator
AN6
AN7
Sample-and-hold circuit
ADI
interrupt
signal
[Legend]
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
ADDRE: A/D data register E
ADDRF: A/D data register F
ADDRG: A/D data register G
ADDRH: A/D data register H
Figure 21.1 Block Diagram of A/D Converter
Rev. 1.00 Mar. 25, 2008 Page 1034 of 1868
REJ09B0372-0100