SH7205 Datasheet, PDF (1287/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Bit
15 to 0
Bit Name
Initial
Value R/W
TRNCNT[15:0] H'0000 R/W
Description
Transaction Counter*
After the total number of packets to be received is
set in these bits for a receiving pipe, setting the
TRENB bit to 1 allows this module to perform the
control explained in the description of the TRENB bit.
Indicates the specified number of transactions if
TRENB = 0.
Indicates the current value of the transaction counter
if TRENB = 1.
This module increments the value of TRNCNT by
one when all of the following conditions (a) to (c) are
satisfied on receiving the packet.
(a) TRENB is 1.
(b) (TRNCNT set value ≠ current counter value + 1)
on receiving the packet.
(c) The payload of the received packet agrees with
the set value in the MXPS bits.
This module clears the value of these bits to 0 when
any of the following conditions are satisfied.
1. All of conditions (a) to (c) are satisfied.
(a) TRENB is 1.
(b) (TRNCNT set value = current counter value +
1) on receiving the packet.
(c) The payload of the received packet agrees
with the set value in the MXPS bits.
2. Both of conditions (a) and (b) are satisfied.
(a) TRENB is 1.
(b) This module has received a short packet.
3. Both of conditions (a) and (b) are satisfied.
(a) TRENB is 1.
(b) TRCLR has been set to 1.
When written:
Specifies the number of transactions to be
transferred by DMA.
Rev. 1.00 Mar. 25, 2008 Page 1255 of 1868
REJ09B0372-0100