SH7205 Datasheet, PDF (728/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
14.5 Usage Notes
Pay attention to the following points when using the WDT in either the interval timer or watchdog
timer mode.
14.5.1 Timer Variation
After timer operation has started, the period from the power-on reset point to the first count up
timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The
shortest such time period is thus one cycle of the peripheral clock, Pφ, while the longest is the
result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent
increment is in accordance with the selected frequency division ratio. Accordingly, this time
difference is referred to as timer variation.
14.5.2 Prohibition against Setting H'FF to WTCNT
When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred.
Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or WDT reset will occur
immediately, regardless of the current clock selection by the CKS[2:0] bits.
14.5.3 Interval Timer Overflow Flag
The IOVF bit in WTCSR cannot be cleared when the value in WTCNT is H'FF. Clear the IOVF
bit when the value in WTCNT is set to H'00 or the value other than H'FF is rewritten.
14.5.4 System Reset by WDTOVF Signal
If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly.
Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To
reset the entire system with the WDTOVF signal, use the circuit shown in figure 14.6.
Rev. 1.00 Mar. 25, 2008 Page 696 of 1868
REJ09B0372-0100