SH7205 Datasheet, PDF (147/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
(1) Crystal Oscillator
The crystal oscillator is an oscillation circuit in which the crystal resonator is connected to the
XTAL/EXTAL pin or USB_X1/USB_X2 pin. This can be used according to clock operating
mode.
(2) Divider 1
Divider 1 divides the frequency of the clock from the EXTAL pin or CKIO pin, or the input clock
from the USB_X1 pin. The division ratio depends on clock operating mode.
(3) PLL Circuit
PLL circuit multiplies the frequency of the input clock from the crystal oscillator or EXTAL pin,
the clock from the CKIO pin, or the input clock from the USB_X1 pin by 12 or 16.
The multiplication rate is set by the frequency control register. When this is done, the phase of the
rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge
of the CKIO pin.
The input clock to be used depends on clock operating mode. Clock operating mode is specified
using the MD_CLK0 and MD_CLK1 pins. For details on clock operating mode, see table 5.2.
(4) Divider 2
Divider 2 generates a clock signal whose operating frequency can be used for the internal clock or
the peripheral clock. The division ratio is set by the frequency control register.
(5) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the MD_CLK0 and
MD_CLK1 pins and the frequency control registers 0 and 1 (FRQCR0 and FRQCR1).
(6) Standby Control Circuit
The standby control circuit controls the states of the on-chip oscillation circuit and other modules
in power-down modes.
In addition, the standby control register is provided to control power-down mode of other
modules. For details on the standby control register, see section 30, Power-Down Modes.
Rev. 1.00 Mar. 25, 2008 Page 115 of 1868
REJ09B0372-0100