SH7205 Datasheet, PDF (735/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Realtime Clock (RTC)
15.3.1 64-Hz Counter (R64CNT)
R64CNT indicates the state of the divider circuit between 64 Hz and 1 Hz.
Reading this register, when carry from 128-Hz divider stage is generated, sets the CF bit in the
RTC control register 1 (RCR1) to 1 so that the carrying and reading 64 Hz counter are performed
at the same time is indicated. In this case, the R64CNT should be read again after writing 0 to the
CF bit in RCR1 since the read value is not valid.
After the RESET bit or ADJ bit in the RTC control register 2 (RCR2) is set to 1, the RTC divider
circuit is initialized and R64CNT is initialized.
BIt: 7
-
Initial value: 0
R/W: R
6
5
4
3
2
1
0
1Hz 2Hz 4Hz 8Hz 16Hz 32Hz 64Hz
-
-
-
-
-
-
-
RRRRRRR
Initial
Bit Bit Name Value
R/W Description
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
1 Hz
5
2 Hz
Undefined R
Undefined R
Indicate the state of the divider circuit between
64 Hz and 1 Hz.
4
4 Hz
Undefined R
3
8 Hz
Undefined R
2
16 Hz
Undefined R
1
32 Hz
Undefined R
0
64 Hz
Undefined R
Rev. 1.00 Mar. 25, 2008 Page 703 of 1868
REJ09B0372-0100