SH7205 Datasheet, PDF (355/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(8) Deep-Power-Down Mode
SDRAMC supports deep-power-down mode for SDRAM. In deep-power-down mode, it issues a
deep-power-down command to drive the CKE signal low.
To perform transition to and recovery from deep-power-down mode, use the SDRAM deep-
power-down control register (SDDPDCNT).
Setting the DDPD bit to 1 causes SDRAM0 and SDRAM1 in SDRAM to enter deep-power-down
mode. Clearing the DDPD bit to 0 causes SDRAMC to recover from deep-power-down mode.
After recovery from deep-power-down mode, SDRAMC issues a deep-power-down exit command
to drive the CKE signal high.
After waiting for the duration designated for the SDRAM being used after recovery from deep-
power-down mode, execute an initialization sequence.
CKIO
SDRAMC deep-power-down mode
CKE
SDRAM command
DPD
Deep-power-down command
DPDX
Deep-power-down exit command
Figure 10.14 SDRAMC Deep-Power-Down Mode
Rev. 1.00 Mar. 25, 2008 Page 323 of 1868
REJ09B0372-0100