SH7205 Datasheet, PDF (480/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
• Cycle-stealing transfer mode
Bus clock
DMA (S)
DMA (D)
(SACT = 0) DMAACTS_N
(SACT = 1) DMAACTS_N
(DACT = 0) DMAACTD_N
(DACT = 1) DMAACTD_N
DMAACK_N
Single operand transfer
(0 wait)
RD1
RD2
WR1
WR2
• Pipelined transfer mode
Bus clock
DMA (S)
DMA (D)
(SACT = 0) DMAACTS_N
(SACT = 1) DMAACTS_N
(DACT = 0) DMAACTD_N
(DACT = 1) DMAACTD_N
DMAACK_N
Single operand transfer
(0 wait)
RD1 RD2 RD3 RD4
WR1 WR2 WR3 WR4
[Legend]
DMA (S): DMA source data transfer cycle on DMA read bus
DMA (D): DMA destination data transfer cycle on DMA write bus
Figure 11.12 Output Timing of DMA Acknowledge Signal and DMA-active signals
Rev. 1.00 Mar. 25, 2008 Page 448 of 1868
REJ09B0372-0100