SH7205 Datasheet, PDF (1104/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.3 Register Descriptions
Table 23.2 shows the FLCTL register configuration.
Table 23.2 Register Configuration of FLCTL
Register Name
Abbreviation R/W
Common control register
FLCMNCR R/W
Command control register FLCMDCR R/W
Command code register
FLCMCDR R/W
Address register
FLADR
R/W
Address register 2
FLADR2
R/W
Data register
FLDATAR
R/W
Data counter register
FLDTCNTR R/W
Interrupt DMA control register FLINTDMACR R/W
Ready busy timeout setting FLBSYTMR R/W
register
Ready busy timeout counter FLBSYCNT R
Data FIFO register
FLDTFIFO R/W
Control code FIFO register FLECFIFO R/W
Transfer control register
FLTRCR
R/W
4-symbol ECC processing
result register 1
FL4ECCRES1 R
4-symbol ECC processing
result register 2
FL4ECCRES2 R
4-symbol ECC processing
result register 3
FL4ECCRES3 R
4-symbol ECC processing
result register 4
FL4ECCRES4 R
4-symbol ECC control register FL4ECCCR R/W
4-symbol ECC error count
register
FL4ECCCNT R/W
Initial Value
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'00000000
H'xxxxxxxx
H'xxxxxxxx
H'00
H'03FF03FF
H'03FF03FF
H'03FF03FF
H'03FF03FF
H'00000000
H'00000000
Address
H'FFFEC800
H'FFFEC804
H'FFFEC808
H'FFFEC80C
H'FFFEC83C
H'FFFEC810
H'FFFEC814
H'FFFEC818
H'FFFEC81C
H'FFFEC820
H'FFFEC850
H'FFFEC860
H'FFFEC82C
H'FFFEC880
H'FFFEC884
H'FFFEC888
H'FFFEC88C
H'FFFEC890
H'FFFEC894
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
8
32
32
32
32
32
32
Rev. 1.00 Mar. 25, 2008 Page 1072 of 1868
REJ09B0372-0100