SH7205 Datasheet, PDF (146/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
Figure 5.1 shows a block diagram of the clock pulse generator.
On-chip oscillator
XTAL
EXTAL
USB_X2
USB_X1
Divider 1
×1
× 1/2
× 1/4
PLL circuit
(× 12, 16)
Crystal
oscillator
Crystal
oscillator
Divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
× 1/8
× 1/12
CKIO
CPU 0 internal clock
(I0φ Max.: 200MHz)
CPU 1 internal clock
(I1φ Max.: 200MHz)
Bus clock
(Bφ Max.: 66.67MHz)
Peripheral clock
(Pφ Max.: 33.33MHz)
MD_CLK1
MD_CLK0
Clock frequency control circuit
CPG control unit
Standby control circuit
FRQCR0 FRQCR1
Bus interface
Peripheral bus
[Legend]
FRQCR0: Frequency control register 0
FRQCR1: Frequency control register 1
Figure 5.1 Block Diagram of Clock Pulse Generator
Rev. 1.00 Mar. 25, 2008 Page 114 of 1868
REJ09B0372-0100