SH7205 Datasheet, PDF (1102/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
Figure 23.1 shows a block diagram of the FLCTL.
DMAC
Peripheral bus
INTC
32
DMA transfer
requests (2 lines)
Peripheral bus interface
32 32
32 32
Interrupt requests
(4 lines)
FLCTL
FIFO
256 bytes
3-symbol
ECC
Registers
4-symbol
ECC
State
machine
QTSEL
FCKSEL
Transmit/
receive
control
×1
CPG
FCLK _×1/2
×1/4 ^{Peripheral clock}
8
8
Flash memory
interface
Note: FCLK is the operating clock for flash memory interface signals.
The division ratio is specified by register FLCMNCR.
8
Control signal
AND/NAND
Flash memory
Figure 23.1 FLCTL Block Diagram
Rev. 1.00 Mar. 25, 2008 Page 1070 of 1868
REJ09B0372-0100