SH7205 Datasheet, PDF (723/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
14.3.4 Notes on Register Access
The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and
watchdog reset control/status register (WRCSR) are more difficult to write to than other registers.
The procedures for reading or writing to these registers are given below.
(1) Writing to WTCNT and WTCSR
These registers must be written by a word transfer instruction. They cannot be written by a byte or
longword transfer instruction.
When writing to the WTCNT, set the upper byte to H'5A and transfer the lower byte as the write
data, as shown in figure 14.2. When writing to the WTCSR, set the upper byte to H'A5 and
transfer the lower byte as the write data. This transfer procedure writes the lower byte data to the
WTCNT or WTCSR.
Writing to WTCNT
15
Address: H'FFFE0002
Address: H'FFFE000A
H'5A
87
0
Write data
Writing to WTCSR
15
Address: H'FFFE0000
Address: H'FFFE0008
H'A5
87
0
Write data
Figure 14.2 Writing to WTCNT and WTCSR
(2) Writing to WRCSR
WRCSR must be written by a word access to its address. It cannot be written by byte transfer or
longword transfer instructions.
Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are
different, as shown in figure 14.3.
To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower
byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the
RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The
values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively.
The WOVF bit is not affected.
Rev. 1.00 Mar. 25, 2008 Page 691 of 1868
REJ09B0372-0100