SH7205 Datasheet, PDF (479/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.9 DMA Acknowledge Signal Output and DMA-Active Signal Output
(1) LSI Internal Signals
The DMAC outputs the DMA acknowledge signal (DMAACK_N) and the DMA-active signals
(DMAACTS_N/DMAACTD_N) for the source and destination when a DMA request is accepted
or DMA transfer is performed. These signals are LSI internal signals, so they cannot be monitored
from outside the LSI. An on-chip peripheral module that requested DMA transfer recognizes that a
DMA transfer request has been accepted and DMA transfer is being performed by monitoring
these signals.
• DMA-active signals
Outputs of DMAACTS_N and DMAACTD_N are enabled by setting the DMA-active signal
output control bits (SACT/DACT) for source and destination in the DMA mode register of the
corresponding channel.
If SACT is set to 1, an active DMAACTS_N signal is output when read access is made.
If DACT is set to 1, an active DMAACTD_N signal is output when write access is made.
• DMA acknowledge signal
DMAACK_N is output during the period from start of single operand transfer to end of single
operand transfer.
Figure 11.12 shows the output timing of the DMA acknowledge signal and DMA-active signals.
Rev. 1.00 Mar. 25, 2008 Page 447 of 1868
REJ09B0372-0100