SH7205 Datasheet, PDF (1221/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
6
EOFERR 0
R/W*¹ PORT1 EOF Error Detection Interrupt Status
This bit is set to 1 when the communication on
PORT1 does not end at the EOF2 timing defined by
USB Specification 2.0.
After detecting an EOFERR interrupt, this module
performs control described below (irrespective of the
setting of the corresponding interrupt enable bit).
Terminate all the pipes in which communications on
PORT1 are currently carried out and perform re-
enumeration of PORT1.
(1) Modifies the UACT bit for PORT1 to 0.
(2) Puts PORT1 into the idle state.
0: EOFERR interrupt not generated
1: EOFERR interrupt generated
5 to 0 
Undefined R
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Notes: 1. Only 1 can be written to.
2. The interrupts generated by the status transitions indicated by each bit in this register
should only be enabled when the host controller function is selected.
3. This module detects the change in the status indicated by the BCHG bit even while the
clock supply is stopped (while SCKE is 0), and outputs the corresponding interrupt
request as long as it is enabled. Clearing the status should be done after enabling the
clock supply.
Rev. 1.00 Mar. 25, 2008 Page 1189 of 1868
REJ09B0372-0100