SH7205 Datasheet, PDF (428/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit
5 to 0
Initial
Bit Name Value R/W
DCTG[5:0] 000000 R/W
Description
(Continued)
001101: MTU2_2
001110: MTU2_3
001111: MTU2_4
010000: IIC3_0 reception
010001: IIC3_0 transmission
010010: IIC3_1 reception
010011: IIC3_1 transmission
010100: IIC3_2 reception
010101: IIC3_2 transmission
010110: IIC3_3 reception
010111: IIC3_3 transmission
011000: SCIF_0 reception
011001: SCIF_0 transmission
011010: SCIF_1 reception
011011: SCIF_1 transmission
011100: SCIF_2 reception
011101: SCIF_2 transmission
011110: SCIF_3 reception
011111: SCIF_3 transmission
100000: SCIF_4 reception
100001: SCIF_4 transmission
100010: SCIF_5 reception
100011: SCIF_5 transmission
100100: SSIF_0 transmission/reception
100101: SSIF_1 transmission/reception
100110: SSIF_2 transmission/reception
100111: SSIF_3 transmission/reception
101000: SSIF_4 transmission/reception
101001: SSIF_5 transmission/reception
101010: SSU_0 reception
101011: SSU_0 transmission
Rev. 1.00 Mar. 25, 2008 Page 396 of 1868
REJ09B0372-0100