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SH7205 Datasheet, PDF (172/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Section 6 Exception Handling
Exception Sources
Vector
Receipt CPU
Numbers Vector Table Address Offset Selection*1
Integer division exception (overflow) 18
H'00000048 to H'0000004B Each CPU
Sleep error
19
H'0000004C to H'0000004F User selection A
(Reserved by system)
20
H'00000050 to H'00000053 
Inter-processor interrupt
(CPU0, CPU1)
21
H'00000054 to H'00000057 Each CPU
:
:
28
H'00000070 to H'00000073
(Reserved by system)
29
H'00000074 to H'00000077 
:
:
31
H'0000007C to H'0000007F
Trap instruction (user vector)
32
H'00000080 to H'00000083 Each CPU
:
:
63
H'000000FC to H'000000FF
External interrupt (IRQ, PINT),
64
on-chip peripheral module*2
:
H'00000100 to H'00000103
:
User selection B
255
H'000003FC to H'000003FF
Notes: 1. Both CPUs: Indicates that exception handling is performed on both CPU0 and CPU1.
Each CPU: Indicates that exception handling is performed on CPU0 when the exception
source occurred on CPU0 or performed on CPU1 when the exception source occurred
on CPU1.
User selection A: Indicates that only CPU0, only CPU1, or both CPU0 and CPU1 can
be selected to perform exception handling.
User selection B: Indicates that only CPU0 or only CPU1 can be selected to perform
exception handling.
2. The vector numbers and vector table address offsets for each external interrupt and on-
chip peripheral module interrupt are given in table 7.4 in section 7, Interrupt Controller
(INTC).
Table 6.4 Calculating Exception Handling Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, sleep errors, register Vector table address = VBR + (vector table address offset)
bank errors, interrupts, instructions
= VBR + (vector number) × 4
Notes: 1. Vector table address offset: See table 6.3.
2. Vector number: See table 6.3.
Rev. 1.00 Mar. 25, 2008 Page 140 of 1868
REJ09B0372-0100