SH7205 Datasheet, PDF (159/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
(2) FRQCR1
FRQCR1 is a 16-bit readable/writable register used to specify the frequency division ratio of the
CPU1 internal clock (I₁φ). The FRQCR1 register should be changed only from CPU1.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
IFC[1:0]
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0 0/1* 0/1* 0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R
R
R
R
Initial
Bit
Bit Name Value R/W Description
15 to 6 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
5, 4
IFC[1:0] 10/01* R/W Division Ratio of CPU1 Internal Clock Frequency (I₁φ)
Specify the division ratio for the CPU1 internal clock, which
is used in division of the output frequency of the PLL
circuit.
• Clock modes 0, 1, and 2
00: × 1
01: × 1/2
10: × 1/3 (initial value)
11: Reserved (setting prohibited)
• Clock mode 3
00: × 1
01: × 1/2 (initial value)
10: × 1/3
11: Reserved (setting prohibited)
3 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * The initial value depends on clock mode.
Rev. 1.00 Mar. 25, 2008 Page 127 of 1868
REJ09B0372-0100