SH7205 Datasheet, PDF (1674/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 32 List of Registers
Module
Name Register Name
Abbreviation
Number
of Bits Address
Access
Size
ATAPI ATAPI control register
ATAPI_CONTROL
32
H'FFFECC80 32
ATAPI status register
ATAPI_STATUS
32
H'FFFECC84 32
Interrupt enable register
ATAPI_INT_ENABLE 32
H'FFFECC88 32
PIO timing register
ATAPI_PIO_TIMING 32
H'FFFECC8C 32
Multiword DMA timing register
ATAPI_MULTI_TIMING 32
H'FFFECC90 32
Ultra DMA timing register
ATAPI_ULTRA_
32
H'FFFECC94 32
TIMING
DMA start address register
ATAPI_DMA_START_ 32
ADR
H'FFFECC9C 32
DMA transfer count register
ATAPI_DMA_TRANS_ 32
CNT
H'FFFECCA0 32
ATAPI control 2 register
ATAPI_CONTROL2 32
H'FFFECCA4 32
ATAPI signal status register
ATAPI_SIG_ST
32
H'FFFECCB0 32
Byte swap register
ATAPI_BYTE_SWAP 32
H'FFFECCBC 32
2DG
Blit function setting register for
graphics
GR_BLTPLY
32
H'E8000000 16, 32
Mixing function setting register for
graphics (synchronized with
VSYNC)
GR_MIXPLY
32
H'E8000004 16, 32
Operation status register for
graphics
GR_DOSTAT
32
H'E8000008 16, 32
Interrupt status register for graphics GR_IRSTAT
32
H'E800000C 16, 32
Interrupt mask control register for GR_INTMSK
graphics
32
H'E8000010 16, 32
Interrupt reset control register for
graphics
GR_INTDIS
32
H'E8000014 16, 32
DMAC-request control register for GR_DMAC
graphics
32
H'E8000020 16, 32
Source A&B read-in-area setting
register for blitter
GR_SABSET
32
H'E8000030 16, 32
Destination C write area setting
register for blitter
GR_DCSET
32
H'E8000038 16, 32
Source E read in-area setting
register for output block
(synchronized with VSYNC)
MGR_SESET
32
H'E8000040 16, 32
Rev. 1.00 Mar. 25, 2008 Page 1642 of 1868
REJ09B0372-0100