SH7205 Datasheet, PDF (1118/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.3.8 Interrupt DMA Control Register (FLINTDMACR)
FLINTDMACR is a 32-bit readable/writable register that enables or disables DMA transfer
requests or interrupts. A transfer request from the FLCTL to the DMAC is issued after each access
mode has been started.
Bits 9 to 5 are the flag bits that indicate various errors occurred in flash memory access and
whether there is a transfer request from the FIFO. Only 0 can be written to these bits. To clear a
flag, write 0 to the target flag bit and 1 to the other flag bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
4ECE ECER
INTE INTE
-
-
FIFOTRG
[1:0]
AC1 AC0 DREQ1 DREQ0
CLR CLR EN EN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R
R R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EC ST BTO TRR TRR STER RBER TE TR TR
ERB ERB ERB EQF1 EQF0 INTE INTE INTE INTE1 INTE0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 26 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
25
4ECEINTE 0
R/W 4-Symbol ECC Pattern Generation End Interrupt Enable
Enables or disables an interrupt to CPU by 4-symbol
ECC pattern generation end.
0: Disables an interrupt to CPU by 4-symbol ECC
pattern generation end.
1: Enables an interrupt to CPU by 4-symbol ECC
pattern generation end.
24
ECERINTE 0
R/W ECC Error Interrupt Enable
Enables or disables an interrupt to CPU when ECC
error occurs.
0: Disables an interrupt to CPU when an ECC error
occurs
1: Enables an interrupt to CPU when an ECC error
occurs
Rev. 1.00 Mar. 25, 2008 Page 1086 of 1868
REJ09B0372-0100