SH7205 Datasheet, PDF (860/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
(4) Data Transmission/Reception
Figure 17.9 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer
clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (SSERI) has occurred,
at this time, the data transmission/reception is stopped. While the ORER bit in SSSR is set to 1,
transmission/reception is not performed. To resume the transmission/reception, clear the ORER bit
to 0.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bit to 1.
Rev. 1.00 Mar. 25, 2008 Page 828 of 1868
REJ09B0372-0100