SH7205 Datasheet, PDF (260/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 User Break Controller (UBC)
8.3.4 Break Data Mask Register (BDMR)
BDMR is a 32-bit readable/writable register. BDMR specifies the bits to be masked of the break
data bits specified by BDR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 0
BDM31 to H'00000000 R/W
BDM0
Break Data Mask
Specify bits to be masked of the break data bits
specified by BDR (BD31 to BD0).
0: Break data bit BDn is included in the break condition.
1: Break data bit BDn is masked and not included in the
break condition.
Note: n = 31 to 0
Notes: 1. Set the operand size when specifying a value on a data bus as the break condition.
2. When the byte size is selected as a break condition, the same byte data must be set in
bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDMR as the break mask data. Similarly,
when the word size is selected, the same word data must be set in bits 31 to 16 and 15
to 0.
Rev. 1.00 Mar. 25, 2008 Page 228 of 1868
REJ09B0372-0100